The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique that is effectively applied to a system LSI (large scale integrated circuit) including a nonvolatile memory such as a mask ROM (read only memory).
The present inventors have studied the following techniques, for example, in the ROM that is equipped in the system LSI.
For example, there exists a ROM equipped in the system LSI in which the word configuration of the ROM is mainly medium-scale and large-scale, and in order to obtain stable and high-speed operation, a memory cell array is of a complementary bit line structure to conduct read operation at high speed by a differential sense amplifier. The ROM of the complementary bit line structure includes memory cells, word lines, complementary bit lines, and differential sense amplifiers that are coupled with the complementary bit lines. Each of the memory cells includes a pair of first and second MOS transistor having gate electrodes coupled with the same word line, respectively. One source/drain electrodes of the first and second MOS transistors are coupled with the corresponding bit lines of complementary bit lines BL and BLB, separately. The other source/drain electrode of the first MOS transistor is coupled with a voltage signal line (common source line) to which a given voltage is applied, and the other source/drain electrode of the second MOS transistor is brought in a floating state.
As a method of writing data in the above ROM, there is a method in which the presence/absence of an electric coupling is produced in the source or drain of an NMOS transistor according to the presence/absence of a through-hole between a first metal layer and a second metal layer. Also, there is a method in which the presence/absence of the electric coupling is produced according to the presence/absence of a through-hole between a diffusion layer and the first metal layer.
FIG. 18 shows an example of the configuration of the ROM memory cell that has been studied as the premise of the present invention. FIG. 18 is an equivalent circuit showing a memory cell for two bits and its coupling. The real memory array is configured in such a manner that the memory cells are arranged and coupled on the array in accordance with a required word configuration and column configuration. In FIG. 18, each of MC(1) and MC(2) corresponds to the memory cell for one bit, and the gates of the MOS transistors that forms the respective memory cells are coupled with word lines WL0 and WL1, respectively. Also, the drains of the MOS transistors within the memory cell are coupled with bit lines BLB and BL. Any one source of the pair of transistors within the cell memory is coupled with a common source line CS by the provision of a CONTACT layer on a layout pattern. That is, a ROM perforation layer is a contact (CONTACT) layer, and information is written according to the provision of the contact layer on which source electrode of the two MOS transistors. With the coupling the common source line CS with the source of any one transistor, any one of the bit lines BLB and BL is coupled with the common source line CS when any one of the word lines WL0 and WL1 is selected, thereby making it possible to induce a potential change in the bit line BLB or BL to read the memory cell information. More specifically, when the word line WL0 is made high level, and the common source line CS is made low level, the potential of BLB in the bit lines BL and BLB that have been precharged to the high level drops. The potential change in the BLB is amplified by the sense amplifier, thereby enabling the memory cell information to be read. Likewise, when the word line WL1 is made high level, and the common source line CS is made low level, the potential of BL in the bit lines BL and BLB drops to read the information.
FIGS. 19(a) and 19(b) show the layout diagrams of the ROM memory cell for two bits corresponding to the equivalent circuit shown in FIG. 18. FIG. 19(a) is a diagram showing the layout pattern of the diffusion layers (Diffusion) that form the MOS transistor, gate layers (GATE), the first metal layers (Metal1) that are extraction electrodes of the sources and the drains, and the contact layers (CONTACT) that couple the diffusion layers with the first metal layers. The two contact layers and the first metal layer which are positioned at the center portion are layers for coupling the drain of the MOS transistor with the bit lines BL and BLB. The gate layers (GATE) that are positioned at both sides of the center portion form the word lines WL0 and WL1, respectively. Further, the contact layers and the first metal layers which are arranged at the outer side thereof are layers for coupling any one source electrode of the paired upper and lower MOS transistors with the common source line CS. That is, the ROM perforation layer is the contact (CONTACT) layer, and the information is written according to the provision of the contact layer on which source electrode of the two MOS transistors. The gate layers that are formed at the outer side thereof are separation gates for separation from the MOS transistors of the adjacent memory cells.
FIG. 19(b) is a diagram showing the layout pattern of the upper layer of FIG. 19(a). The bit lines BL and BLB are formed of the second metal layers (Metal2), and coupled with the first metal layers that are the source electrodes of the MOS transistors of lower layers through via 1 (Via1). The common source lines CS are also formed of the second metal layers (Metal2), and coupled with the first metal layers that are the drain electrodes of the MOS transistors of the lower layers through the via 1 (Via1). The word lines WL0 and WL1 are formed of third metal layers (Metal3). The word lines WL0 and WL1 that are formed of the gate layers of FIG. 19(a) are coupled with the word lines WL0 and WL1 that are formed of the third metal layers of FIG. 19(b) in a word shunt pattern not shown in the layouts of FIGS. 19(a) and 19(b). The word shunt pattern is regularly arranged according to the necessity of a reduction in the word line resistor, for example, every four bits or eight bits.
FIG. 20 shows an example of the coupling of the ROM memory cell with the differential sense amplifier. The complementary bit lines BL and BLB are coupled with global bit lines gb1 and gb1b through a column switch. The global bit lines gb1 and gb1b are coupled with the input terminals of the differential sense amplifier, an equalizer circuit, and an output latch.
FIG. 21 shows a coupling diagram of the ROM memory cell. As shown in FIG. 21, any one of the MOS transistors is coupled with the CS line by ROM perforation to store data. The MOS transistor that has not been subjected to ROM perforation serves as a switch that changes the potential of the bit line b1 or b1b even if the wordline w1 is selected. However, the diffusion capacities of the MOS transistors that are coupled with the bit lines b1 and b1b are equal to each other. As a result, the input capacity of the differential sense amplifier becomes balanced. This enables the stable high-speed read operation.
FIG. 22 shows a timing chart of the read operation of the ROM memory cell through a common source control system that has been studied as the premise of the present invention. The read operation starts from the operation of taking an address within a control circuit in synchronism with a leading edge of a clock. One of the word line signals w1 is driven to high level from a decoder on the basis of an address signal and a read instruction command which are output from the control circuit. In this operational example, the word line w1 n+3 is selected. Also, one of Y switch control signals yse [n:0] is driven to the high level, and the bit lines b1 and b1b and the global bit lines gb1 and gb1b are coupled with each other through a Y switch. On the other hand, the common source line CS is driven to low level. The word line w1 n+3 is driven to the high level, and the common source line CS is driven to the low level, as a result of which the potential difference between the bit lines b1 and b1b increases according to information that has been written in the memory cell. When the potential difference between the bit lines b1 and b1b increases to some degree, a sense amplifier enable signal sae is output from the control circuit to conduct the amplifying operation by the sense amplifier. Then, the potential difference between the global bit lines gb1 and gb1b increases to the high level and the low level. When the potential difference between the global bit lines gb1 and gb1b increases, the output latch is inverted according to the read data. When the read data is in an initial state or identical with the previous read data, the output latch is not inverted, and holds the data.
In the ROM of this configuration, because both of the common source line CS that is coupled with the source node of the memory cell, and the bit lines b1 and b1b which are coupled with the drain node thereof are set to Vdd during a period other than the read time, a leak current at the memory portion is remarkably reduced. Also, when the CS select timing is set after the word is selected, an affect (leak current) of the unselected memory cell can be reduced.
As the technique related to the above ROM, there is, for example, a technique disclosed in Japanese Unexamined Patent Publication No. 2005-327339.